1. Field of the Invention
This invention relates to a standard-cell type semiconductor integrated circuit device with a mixed arrangement of standard cells differing in cell height.
2. Description of the Related Art
In a standard-cell type semiconductor integrated circuit device, a large number of standard cells are designed to have the same height in order that they can be arranged closely with high density.
Making the cell height small is effective in realizing high integration of standard cells. However, when large-sized transistors are needed for high-speed operation, cells with a small height require a large number of small-sized transistors to be arranged and connected in parallel to form large-sized transistors.
When a plurality of transistors are arranged and connected in parallel to form large-sized transistors, each cell has more frontage than height, or is oblong. As a result, more inefficient parts area are produced. They include the SDG (source, drain, and gate) regions in n-channel and p-channel MOS transistors, and the boundary between the p-well and the n-well.
Therefore, cells with more height than frontage, or lengthwise cells, are effective in terms of area in configuring large-sized transistors.
When standard cells greatly differing in cell height are arranged in the same column, the position of the boundary between the p-well and the n-well in a standard cell with a small cell height differs from that in a standard cell with a large cell height. This makes it difficult to arrange standard cells differing in cell height in the same column.
Accordingly, in one column, only standard cells with the same height are arranged. In the standard cells with the same cell height, transistors of the same size are provided. In the standard cells differing in cell height, transistors differing in size according to cell height are provided. Transistors differing in size differ in characteristics.
As described above, since only standard cells with the same cell height are arranged in one column, standard cells with a large cell height which need large-sized transistors and are required to operate at high speeds are arranged in one cell block and standard cells with a small cell height which are not required to operate at high speeds are arranged in another cell block in the prior art semiconductor integrated circuit device.
In a semiconductor integrated circuit device in which a plurality of cell blocks are provided, when signal lines are provided so as to cross cell blocks, the line length becomes long, which delays the signals. To overcome this problem, buffer amplifiers, called repeaters, are inserted in the signal lines to reduce the delay time in the signals caused by the lines.
However, in the case where a plurality of repeaters are inserted in the path of one signal, when the plurality of repeaters are provided in different cell blocks where standard cells differing in cell height are arranged, the transistors differ in characteristics, because the transistors arranged in the standard cells differ in size. As a result, the delay time of the signal in the signal path in which each repeater is inserted differs from one signal path to another. Consequently, the desired characteristic might not be obtained by the circuit that receives the signal.
As described above, the size of transistors arranged in the standard cells is determined by the cell height of the standard cells. As a result, circuits composed of standard cells in different cell blocks in which standard cells differing in cell height are provided differ in characteristics. This makes it impossible to obtain the desired characteristics. Thus, a solution to this problem has been desired.